1. Field of the Invention
The present invention generally relates to an accessing method and a microinstruction control type microprocessor. More specifically, the invention is directed to a microprocessor employing a so-called "pointer register" accessible to a desired register in register groups without receiving a direct instruction by microinstructions, and also to an accessing method thereof.
2. Description of the Related Art
In general, a control space for defining relationships between predetermined addresses and registers in various registers such as control registers and general-purpose registers is constituted by allocating the specific addresses to each register of these registers, and a specific, or desirable register is accessed based upon a decoded microinstruction in order that information is either stored into, or read out from a desired register which is has named by the specific address in a conventional microprocessor.
Very recently, a so-called "TRON (The Real-Time Operating System Nucleus)" computer operating system has been proposed. In connection with this "TRON" operating system, various types of microprocessors have been developed. These "TRON" operating system and relevant microprocessors are described in, for instance, "TRON Project 1987" Open-Architecture Computer System, by K. Sakamura, issued from Springer-Verlay publisher Tokyo 1987, on pages 291 to 308.
In FIG. 1, there is shown an internal arrangement of one conventional microprocessor applicable to the above-described "TRON" operating system. FIG. 2A represents an overall address map on typical addresses and respective register groups, which constitute a control space that has been introduced in the "TRON" system, and FIG. 2B illustrates another map of addresses which are indicated by way of the hexadecimal notation and allocated to each register in the general-purpose register group. As is apparent from the address maps shown in FIGS. 2A and 2B, a large quantity of addresses for the control space are utilized in the "TRON" operating system.
A register accessing operation of the conventional microprocessor shown in FIG. 1 will now be described. That is, when data is stored or read from a specific register in a general-purpose register group 8 which has been designated by a STC (store-control-space) instruction, a sequential comparison is made between an address instructed by an address register 3 and 15 pieces of addresses of the control space, e.g., H'0184 and H'018C which have been allocated to the respective registers in the general-purpose register group 8. Then, when a coincidence occurs in the address comparison operations, the instructed or desired register, for instance, R0 or R1 is accessed for the data storage and/or read purposes which will be discussed later in detail. In the microprocessor illustrated in FIG. 1, two operand registers 5 and 6 for temporarily storing operands are connected to data buses "L-BUS" and "R-BUS". An arithmetic and logic unit (simply referred to as an "ALU") 7 is connected to these operand registers 5 and 6 and to the data buses "L-BUS" and "R-BUS". A first gate 9 is connected to control registers 4 and also to the general-purpose register group 8. A second gate 12 is interposed between the general-purpose register group 8 and the data bus "L-BUS".
Referring now to a flowchart shown in FIG. 3, an accessing operation to a desired register "R0" to "R14" among the general-purpose register group 8 for constituting a control space, will now be described in detail.
When, for instance, contents (data) of a specific register "R0" to "R14" in the general-purpose register group 8 are wanted to be read, the STC instruction is decoded in the instruction decoder 1 so as to obtain a decoded instruction and address data. Then, the microinstruction previously stored in the microinstruction storage unit (ROM) 2 is read in response to the decoded instruction and the read microinstruction is stored in the microinstruction register 4 (see FIG. 1). Thereafter, the general-purpose register group 8 is designated by the selection field "X.sub.2 " of the microinstruction. Furthermore, a specific register, e.g., register R4 shown in FIG. 2B in the register group 8, is designated by the register number instruction field "X.sub.3 ", and thus the operation instructed by the control field "X.sub.1 " is performed. That is, the data is read out from the register R4 in the general-purpose register group 8 and transferred via the data bus "L-BUS" to an external memory (not shown in FIG. 1).
In the flowchart shown in FIG. 3, in a first step ST-1, an address "src" of a source operand of the above-described STC instruction is compared with another address "H'0184" allocated to the first register "R0", indicated in the hexadecimal notation, in the general-purpose register group 8 shown in FIG. 2B. If the first address "src" is coincident (with the second address "H'0184 (in a step ST-2), the contents (data) of the first register "RO" are read out and transferred via the data bus "L-BUS" to the external memory (not shown in detail) in the subsequent step ST-3. To the contrary, if a comparison result is NO in the previous step ST-2, the addressing process is advanced to a next step ST-4. In this step ST-4, a similar comparison is made between the address "src" and a new address "H'018C" of the second register Rl. If this "src" is equal to the new address "H'O18C" (step ST-5), the content of the second register R1 is read and thereafter transferred via the data bus L-BUS to the external memory. However, if the comparison result becomes NO, then an address "H'0194" of the subsequent register R2 is compared with the address "src" in the next step (not shown in detail). Subsequently, such a comparison operation is sequentially executed so as to retrieve a coincident address.
As a consequence, as is apparent from the above-described series of the address accessing operation, such an address accessing operation must be repeated 15 times until the desired specific register finally retrieved in case that the specific register corresponds to a fifteenth register R14. Therefore, the number of steps in the retrieving program is considerably increased.
Furthermore, there is another problem in that a large quantity of microprograms are necessarily required so as to fetch the contents of the register whose address coincides with the address "src" of the STC microinstruction.